The present invention relates generally to computer systems, methods and software, and more particularly, to systems, methods, and software for reducing system management interrupt (SMI) latency while polling in system management mode.
System management interrupt (SMI) handlers typically must wait while polling for a hardware event, such as completion of data transfer for a hardware device. This wait period can cause execution of the SMI handler to be so long that other interrupts are not serviced in a timely fashion.
The system management mode (SMM) is entered when the CPU receives a system management interrupt. The SMI is the highest priority interrupt in the system and while the interrupt is being serviced, no other interrupts are serviced.
In general, the SMI handler is provided by system firmware. The other interrupt handlers are, in general, provided by the operating system. The SMI handler is hidden from the operating system. There are often dozens of possible SMI interrupt sources, hardware and software.
Many times the SMI handler is required to initiate actions, that require it to wait hundreds or thousands of milliseconds. Since the SMI is the highest priority interrupt and no other interrupts can be serviced while in System Management Mode, it is possible that the time spent servicing the SMI could cause other, lower-priority, interrupts to be missed. This can result in disrupted communications, delayed timers, broken-up audio, and the like.
Furthermore, since the SMI handler is hidden from the operating system, it is not possible to use such mechanisms as deferred procedure calls where the operating system or firmware would call again at a lower priority level so that these interrupts could be serviced.
There are several general themes in the prior art for handling difficulties relating to system management interrupt latency.
One is to simply ignore the problem. Since the actual occurrence of such errors is relatively small and since most communication systems have error recovery, no provision is made. This is the system used by most PC firmware solutions.
Another is a Deferred Procedure Call. The high priority interrupt saves the information needed to handle the interrupt and then schedules a deferred procedure call at a lower priority. This means that the time spent at the highest priority is relatively small and other interrupts can be serviced. This is the system used by Windows NT and other desktop operating systems.
Another is a Common Interrupt Handler. All interrupts, including SMI go to the same handler, which then schedules the appropriate event handler at a software-determined priority level and then exits. This is the system used by small real time operating systems (RTOS), such as Minos disclosed in “Operation Systems: Concepts and Design” published by McGraw-Hill© 1987, Milan Milenkovi, for example.
Another uses separate interrupt handlers in SMM. It is technically possible to service interrupts while in SMM. In this case, the interrupts are still serviced and so there is no latency issue.
Another is a specific hardware design. Through hardware design, some systems use SMIs to indicate the end of all long hardware transactions. This eliminates the need for polling. This is used in National Semiconductor integrated chipsets.
There are various disadvantages using the known prior art.
For example, errors do occur. Serial port transmission, USB 2.0 frame interrupts, lost timer ticks and audio break-up are all common symptoms. In many applications, these symptoms cause major operational difficulty.
The problem with the Deferred Procedure Call and the Common Interrupt Handler are that, while outside the SMI handler, the SMI handler is invisible to the operating system. So once scheduled to execute at a lower priority level, the SMI handler can no longer be called.
With regard to the use of separate interrupt handlers in system management mode, firstly, it is technically difficult to re-enable interrupts inside of SMM and there is no guarantee of broad support across CPU manufacturers. Secondly, it requires that, at the time of the SMI, the operating system is ready to service all interrupts. In many cases, SMIs are generated while all other interrupts are disabled temporarily.
Hardware design usually requires that the components of the system are tightly integrated, often by the same manufacturer.
In view of the above, it is an objective of the present invention to provide for systems, methods, and software for reducing system management interrupt latency while polling in system management mode.